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Pull requests: openhwgroup/cv32e40p
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RISC-V ISA Formal Verification files for SiemensEDA OneSpin tool.
Component:Tool-and-build
For issues in the tool and build flow (e.g. Makefile, FuseSoc, etc.)
Component:Verif
For issues in the verification environment or test cases (e.g. for testbench, C code, etc.)
#993
opened May 30, 2024 by
pascalgouedo
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User Manual verification section update.
Component:Doc
For issues in the Documentation (e.g. for README.md files)
#992
opened May 30, 2024 by
pascalgouedo
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[DO NOT MERGE] Break the ALU
Status:Do-not-merge
Pull request that should not be merged (yet)
#703
opened Apr 27, 2022 by
suppamax
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Add FPGA Optimized Register File Version
WAIVED:CV32E40P
Issue does not apply to CV32E40P and is waived
#433
opened Jul 29, 2020 by
ganoam
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Fusesoc and Linter
WAIVED:CV32E40P
Issue does not apply to CV32E40P and is waived
#368
opened Jun 16, 2020 by
wallento
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Fix Verilator simulations
WAIVED:CV32E40P
Issue does not apply to CV32E40P and is waived
#351
opened May 23, 2020 by
wallento
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first version of Synopsys DC script
Status:Do-not-merge
Pull request that should not be merged (yet)
WAIVED:CV32E40P
Issue does not apply to CV32E40P and is waived
#305
opened Apr 10, 2020 by
davideschiavone
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